HOST_PORT_POWER_CONTROL_PRESENT=Val_0x0, HUB_PORT_PERM_ATTACH=Val_0x0, HOST_U2_PORT_DISABLE=Val_0x0, HUB_PORT_OVERCURRENT=Val_0x0
USB Control Register 1
| HUB_PORT_OVERCURRENT | This is the port over-current indication of the root-hub ports 0 (Val_0x0): No over-current 1 (Val_0x1): Over-current |
| HUB_PORT_PERM_ATTACH | Indicates if the device attached to a downstream port is permanently attached or not 0 (Val_0x0): Not permanently attached 1 (Val_0x1): Permanently attached |
| HOST_NUM_U2_PORT | Number of USB 2.0 ports |
| HOST_U2_PORT_DISABLE | USB 2.0 Port Disable Control This bit should either be static (should not change during operation) or change only once from 0x0 to 0x1 during operation and stay at 0x1 after that. 0 (Val_0x0): Port enabled 1 (Val_0x1): Port disabled |
| HOST_PORT_POWER_CONTROL_PRESENT | This bit defines the bit [3] of Capability Parameters (HCCPARAMS). This indicates whether the host controller implementation includes port power control. 0 (Val_0x0): Port does not have port power switches 1 (Val_0x1): Port has port power switches |
| HOST_MSI_ENABLE | This enables the pulse type interrupt signal (one bus clock cycle) interrupt port instead of level-sensitive interrupt. When interfacing to PCIe, this allows the user to easily map interrupt to MSI in the PCIe controller. |
| HOST_LEGACY_SMI_PCI_CMD_REG_WR | PCI command register write: one clock pulse. The PCIe interface needs to generate one clock pulse during PCIe command register write. |
| HOST_LEGACY_SMI_BAR_WR | PCI Base Address Register (BAR) write: one clock pulse. The PCIe interface need to generate one clock pulse during PCIe BAR write. |